Hi All ,
I am revisiting SV Coverage and trying out scenarios which I missed out on earlier .
Here is one such scenario I was thinking of :
A typical race condition in standard Verilog is when a variable is being read as well as written on same event :
always @( posedge clk )
out = < Some_Expression > ;
always @( posedge clk )
sample = out ;
The solution is to use non-blocking assignment .
Although typically race condition isn’t associated with coverage sampling , I was wondering if there could be a possibility .
LRM says :
a coverage point is sampled the instant the clocking event takes place,
If I were to write :
bit clk ;
bit [2:0] a ;
covergroup cg @( posedge clk ) ; // Triggered in Active Region
coverpoint a ;
endgroup
cg cg1 = new() ;
always #5 clk = !clk ;
always @( posedge clk ) a = a + 1 ; // Updated in Active region as well
initial #50 $finish() ;
[Q] As ’ a ’ is sampled and updated on the same posedge , either the previous or updated value could be sampled , right ?
i.e values sampled could either be auto[0] , auto[1] , auto[2] , auto[3] and auto[4] OR auto[1] , auto[2] , auto[3] , auto[4] and auto[5]