Can logic always replace wire or reg in an interface

SystemVerilog
1

Can logic always replace wire or reg in an interface

2

In reply to to_learn_uvm:

logic replaces the antiquated keyword reg everywhere. Both logic and reg are 4-state datatypes that do not necessarily represent a “Register”.

When you write

interface iff(input logic signal);
signal gets implicitly declared as a 4-state wire. See [this link](https://verificationacademy.com/forums/systemverilog/usage-var#reply-42240) for more explanation.

You need to be careful replacing wire with logic with a signal internal to a module or interface. logic variables can only have one continuous assignment. Port connections create continuous assignments to the variables they are connected to even if there are no other assignments to the other side of the port.

module m(output logic p);
// no assignments to p inside m
endmodule 
module top;

logic up;
m inst(.p(up)); // implicit continuous assign up = inst.p

endmodule