Can interface be instantiated in array?

SystemVerilog
1

Hello,

Is the following statement that instantiates an interface into an array valid in LRM? It works on Cadence Xcelium though


Interface my_if;
endinterface

module my_tb;
  my_if  tb_if_inst[2] ();

endmodule

Many thanks.

2

In reply to Michaelotus:

Yes, you can instantiate what looks like an array of modules instances. However, it is not a true array like a variable with a dynamically selected index.