Can anyone help me debug the issue in this code?

class packet;
  
  randc bit [7:0]s_addr;
  randc bit [15:0]e_addr;
  randc bit [2:0]mul_factor;
  randc bit [15:0]addr;
  
  constraint c {e_addr == end_addr(s_addr);}
  
  function bit[15:0] end_addr(bit [7:0]start_addr);
    end_addr = (mul_factor*start_addr);
  endfunction
  
endclass

`include "packet.sv"
module top;
  packet pkt;
  initial
  begin
    pkt = new();
    repeat(1)
    begin
      pkt.randomize() with {s_addr < addr; addr < e_addr;};
      $display("The value of multiplying factor is %0d",pkt.mul_factor);
      $display("The value of starting address is %0d",pkt.s_addr);
      $display("The value of ending address is %0d",pkt.e_addr);
      $display("The value of the address is %0d",pkt.addr);
    end
  end
endmodule

I get fatal error saying :

#    Time: 0 ps  Iteration: 0  Process: /top/#INITIAL#4 File: top.sv
# Fatal error in Module top at top.sv line 9
# 
# HDL call sequence:
# Stopped at top.sv 9 Module top
#

In reply to Ravi007:

Ran code on Edit code - EDA Playground
Error-[IVCB-NORANDC] Illegal use of randc variable
testbench.sv, 10
$unit, “this.s_addr”
The expression contains the variable s_addr of type randc and cannot be used
in solve-before, distribution, unique and function calls.
Change the type of the randc variable or remove it from the expression.

2 errors
Ben Ben@systemverilog.us