Blocking wait statements

SystemVerilog
1

So i have two tasks

task 1 ;
  samples interface signals
  add to a queue
endtask

task 2;
  respond to the queue.
  it has statements like 
  intf.readdata = mem[addr];
  @(posedge intf.clk);
  While responding try to randomly add delays
  if (rand_fact ==1) begin
    intf.readdata = 'hz;
    @(posedge intf.clk)
  end
endtask

Both of these tasks i an running with a third task

task3;
 forever begin
  fork
    task1;
    task2;
  join
 end
endtask

What is happening is my sampling task for some reason does not keeping sampling if rand factor is 1 and read data goes z.
So it seems like task1 . does not work if there is any wait statement in task2 holding the full process.
What is a better way to do this?
am i doing it completely wrong ?

2

In reply to jay.trivedi1988:

You never explain how you want your code to work, only that it doesn’t. Perhaps you want

t

ask3;

  fork
    forever task1;
    forever task2;
  join
 end
endtask