Bit Assigning

SystemVerilog
1

Hi ,
In the below Code , I have tried to assign the particular bit of a variable to another variable.

bit[37:0] addr; // Random 38 bit value from memory chosen.
bit[31:0] temp_a;
bit[5:0] temp_b;
bit[5:0] temp_addr;

// when I have tried to get random value from this range , temp_a = $urandom_range(0,addr[37:0]);
I got error, as randomization is limited to 32bit.
temp_a = $urandom_range(0 , addr[37:0]);
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ncelab: *W,INTWID: Invalid width (38) on argument, (32) expected.

Secondly,I have tried to assign the 6 bit to another variable and try to chose random value but still i got error.

temp_a = $urandom_range(0,addr[31:0]);
temp_b = addr[37:32];
temp_c = $urandom_range(0,temp_b);

temp_addr = $urandom_range(0, temp_b);
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ncelab: *W,INTWID: Invalid width (6) on argument, (32) expected.

So what can i do for this Warning.?

Thanks,
Sandeep Gaur

2

In reply to Sandeep Gaur:

You can harness the power of the SystemVerilog constraint solver.


std::randomize(temp_a) with {temp_a inside {[0:addr]};};
3

In reply to sbellock:

Hi ,
But I want 38 bit value address.

bit [37:0] addr;
bit [37:0] temp_addr;

std::randomize(temp_addr) with {temp_addr inside {[0:addr]};};

can I get a 38 bit random address using this.?

Thanks,
Sandeep Gaur R

4

In reply to Sandeep Gaur:

Did you try it?

5

In reply to dave_59:

Yes Dave , It is working now.

but why I cant get the value using $urandom_range.?

Whether the Randomization is limited to 32 bit for $urandom_range .?

6

In reply to sbellock:

Thanks , it is working now.

7

In reply to Sandeep Gaur:

The return value of $urandom/_ramge is int.

8

In reply to dave_59:

Got it…!!!
Thanks Dave.