Bind with port type logic

SystemVerilog
1

I have a question about the bind usage when the port type is logic.
If port type is not used as logic, then it works as expected, and makes wire-connection. I believe that default_nettype is wire so when the port type is not defined. However, it does not make any connection to dut when the port type is logic.
I am trying to understand why bind does not work when port type is logic in the below scenario. I think this could be a tool issue that I use.

module dut(
  input logic [2:0] a,
  output logic [2:0] b
) ;
  
  assign b = a ;
  
  initial begin 
    $monitor("%t  a = %d  b=%d",$time,a,b); 
  end 
  
endmodule 

module bind_dut(
  input logic [2:0] a,
input logic [2:0] b
);

logic a1 ;  

  always @* begin 
     force a = a1;
  end 
  
  initial begin 
    a1 = '0 ;
    #20;
    a1 = 'dz;
    #30 ;
    a1 = '0 ;
    #10;    
  end   
 
endmodule 

module top ;

  bind dut bind_dut dut_inst(.*);
  
endmodule

Output of Model dut is :
at time 0 , a=x , b-x;

2

Because there is no connection beetween dut and bind dut, and you changing values of bind dut and monitoring values of dut that’s why it gives x x because it takes default values for logic as x.

3

In reply to dyno:
Could you please elaborate on where the connection missing? However, I have identified its tool issue as it works with other tool vendors.

4

In reply to kddholak:

You have run into a tool specific problem. logic is a datatype that applies to both variable and nets. The LRM says input ports default to nets unless the var keyword is used. logic is the default datatype. The following declarations are equivalent.

  input logic [2:0] a,
  input wire logic [2:0] a,
  input wire [2:0] a,
  input [2:0] a,

You tool is treating the declaration as

  input var logic [2:0] a,

That prevents the port from being collapsed and coerced to an inout.