Avoiding non-user defined bins within cross

SystemVerilog
,
1

Hi All ,
For the following code ::


 bit [1:0]  a , b ; 

   covergroup  Covdst ;
   
    a_cp: coverpoint ( a ) 
    {   
      bins  a0  =  { 0 } ; 
    
      bins  a1  =  { 1 } ; 
    }   
    
    b_cp: coverpoint ( b ) 
    {   
       bins  b0  = { 0 } ; 
    
       bins  b1  = { 1 } ; 
    }   
   
   x1: cross a_cp , b_cp 
    {   
       bins  a0b0  =  binsof( a_cp.a0 )  &&  binsof( b_cp.b0 ) ;   
    
       bins  def   =  default ;  //  Avoiding  all  other  cross     
    }
    
   endgroup    
   
  //   Instantiate  covergroup   here  as  part  of  handle  declaration  itself .

I observe compilation error with the above code .
However on checking the LRM I don’t see default bins being termed as illegal when used within cross .

LRM mentions examples using bins / ignore_bins / illegal_bins within cross as legal
( wildcard bins within cross works as well although LRM doesn’t have examples for it )

Have 3 questions in mind ::

(1) Is default illegal within cross ? If yes why is it so ? ( I expected LRM to mention this )

(2) Any work-around for above scenario ?
The above code has 4 cross possible , however my project has 80 cross products
out of which I am interested in 2-3 .

(3) Within cross when defining user-defined bins , is the user limited to use only Select Expressions ( binsof( ) / !binsof( ) ) on right side ?

Thanks.

2

In reply to MICRO_91:

The BNF (syntax) does not allow
default as a select expression. You can accomplish what you want by writing:

   x1: cross a_cp , b_cp 
    {   
      ignore_bins  a0b0  =   ! binsof( a_cp.a0 )  || !  binsof( b_cp.b0 ) ;   
 
    }

However, if you just want a small selection of a cross, it might be easier to define another coverpoint instead of using a cross.

x1: coverpoint a==0 && b ==0  { 
         bins  a0b0  =  { 1'b1 } ; // corrected to only catch "truth"
      }
3

In reply to dave_59:

Thanks Dave , LRM Syntax 19-4 only allows binsof( … ) , !binsof( … ) as a select expression .

x1: coverpoint a==0 && b ==0;

This would generate 2 automatic bins , ’
auto[0] when the expression is false and auto[1] when expression is True .

I believe you meant ::


  x1: coverpoint ( a==0 && b ==0 )
      { 
         bins  a0b0  =  { 1'b1 } ; 
      }

Another way would be concatenation of the 2 variables in coverpoint expression


x1: coverpoint( { a , b } ) 
   {
      bins  a0b0  =  { 2'b00 } ;  //  EDIT  ::  Added  Curly  braces 

      bins  deflt =  default ;  //  Legal  here 
   }