Augmented/Compound assignment and SystemVerilog standards documentation

SystemVerilog
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Hi, I had a problem with a different language in its treatment of augmented assignment (for example +=, plus-equals).
I was throwing a random die reatedly and keeping a count of the number of times that each number from the die was seen in a loop using the following kind of expression (pseudocode):

bin_counter[ roll_die() ] += 1

The language I was using seemed to expand this and execute the following:

bin_counter[ roll_die() ] = ]bin_counter[ roll_die() ] + 1

The two calls to roll_die() could give differing results leading to errors.

I decided to check various languages and found that C, C++ and Python all specify that the array subscript is to be evaluated only once.
On looking at an old SystemVerilog standard, the only one I could google, the above issue was not resolved in the IEEE spec (SystemVerilog 3.1a 2004).

Could someone check if this resolved/applies in the current spec.

Thanks :-)

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In reply to Paddy3118:

The 1800-2017 LRM says the same as the other languages you mention:

An assignment operator is semantically equivalent to a blocking assignment, with the exception that any left-hand index expression is only evaluated once.

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In reply to dave_59:

Thanks. That’s what I wanted to hear.

(I also updated the wikipedia entry on Augmented assignment with a section highlighting the issue).