Assign statement equivalent construct in SystemVerilog

SystemVerilog
1

I am trying to model a Design in SV for verification purpose.

I am looking for construct which works similar to assign statement in verilog but can be used inside class

eg: assign counter_signal = a + b;

I am looking for some construct which works the same but can be used inside a class.

I am assuming, we can not use assign statement in a class

THANKS IN ADVANCE

2

In reply to tejasakulu:

Basically you want to update the counter_signal whenever a or b change.


class cnts_update;
  bit [31:0] a,b;
  bit [32:0] counter_signal;
  
  task run();
    fork
      forever begin
        @(a+b);
        counter_signal = a + b;
      end
    join_none
  endtask
  
endclass


module tbtop;
    
  cnts_update cnts_i;
  initial begin
    cnts_i= new();
    cnts_i.run();
    $monitor("%t, a : %0d, b : %0d, %0d", $time, cnts_i.a, cnts_i.b,  cnts_i.counter_signal);
    
    repeat(20) begin #10; cnts_i.a =$urandom;  cnts_i.b=$urandom; end
  end
  
endmodule