Assign dynamic width

SystemVerilog
1

For example,
I can assign dynamic array.

At beginning by declaration and when I know the size then assign.

  logic                  do_update_check[];
    do_update_check = new [size]; //size - we know the value.

but how can I do the same if I declare ?


    logic                  []do_update_check; //should be width

Thanks,
Alex

2

In reply to alexd555:

The size of an unpacked dynamic array can be set—dynamically; meaning by the execution of a procedural statement at runtime.

The size of an integral packed array (also known as the width) must be set at compile time because the width of an integral value it part of its datatype and cannot be changed at runtime. SystemVerilog is a statically typed language.