Hello guys, I have a question. I know its possible to place assertions in any place of the timed domain in SystemVerilog/UVM Testbench in (Monitor, Interface, or even Scoreboard). I placed some assertions in monitor, and my instructors told me it’s not the appropriate place. and I have placed a state machine in the monitor… which will predict the value state of the DUT and send it to the scoreboard. and the scoreboard is just a compare methods between the predicted value and actual value. Is it wrong or not a standard to place a Reference Model that predict output into the Monitor?
In reply to haithamx15:
I know its possible to place assertions in any place of the timed domain in SystemVerilog/UVM Testbench in (Monitor, Interface, or even Scoreboard)
The term assertion is a statement that a property is true. It can be implemented in straight code (e.g., SV tasks) or SVA. If you meant SVA, then those concurrent assertions are not allowed in classes; see my papers (links below) on creating SVA alternatives using classes.
You are correct in stating that the monitor collects and pre-process the information needed by the scoreboard. So it is OK for a monitor to predict the value state of the DUT and send it to the scoreboard. The scoreboard is just a compare method between the predicted value and actual value. Personally, I believe that the monitor and scoreboard are so closely linked that there is no need to separate them, meaning that you end up with a single unit that does both tasks. I can however see complex cases where the data collection is so complicated that it is s best to separate the collection from the evaluation (or scoreboard). For example, if you are collecting a large image, you may have a monitor that stores that image in an array, and when the frame is collected, you send that array to the scoreboard.
Is it wrong or not a standard to place a Reference Model that predict output into the Monitor? Not IMHO.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
- http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
- “Using SVA for scoreboarding and TB designs”
http://systemverilog.us/papers/sva4scoreboarding.pdf - “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3 - SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment