Assertions

SystemVerilog
1

Hi,

I am unable to understand the difference between a property and a sequence. Can somebody explain??

Thankyou

2

Hello Chandana,

  1. Property is the specific statement like for checking the behavior of DUT and sequence is the combination of Boolean expression.

  2. We can use many sequences in the property but not property in the sequences.

  3. Sequences can be re-usable as per our requirements in property.

  4. We can’t use implication operators in sequences but in property, can be used.

like for e.g.

suppose sequence1, sequence2, sequence2…etc

sequence seq1;

a ##1 b;

endsequence : seq1

sequence seq2;

c ##4 d;

endsequence : seq2

sequence seq3;

a ##4 d;

endsequence : seq3

property p1;

seq1 && seq2 |=> seq3;

endproperty : p1

a_p1 : assert property (@(posedge clk) p1);

property p2;

seq3 && seq2 |=> seq1;

endproperty : p2

a_p2 : assert property (@(posedge clk) p2);

…
So now you see in above examples, we can use many sequences like seq1, seq2, seq3…etc in property p1, p2, …etc as per our requirements.

3

SystemVerilog assertions have 4 layers of definition:

  • Boolean - a combinatorial expression of logic that evaluates true or false at one instant in time
  • Sequence - a finite list of Boolean expressions in linear order of clock cycles. A complex sequence may have parallel branches in the list, but all start at the same time and specify every cycle in order. Basically a sequence tries to match a pattern of Boolean expressions over time with a regular expression
  • Properties - define collections of sequences and define when to start and end the sequence or sequences. It also defines when a sequence is considered to pass or fail.
  • Directive - this creates an instantiation of a property and defines what action should be taken if the property passes or fails.

This is very simplified, but there is a lot more information available on this topic if you search for it.