Assertion Greater or equal than

SystemVerilog
,
1

Hi,

Is this a valid property if I want to check that: error_high >= error_low ?


    logic [9:0] error_low;
    logic [9:0] error_high;

    property error_low_greater_than_error_high;
      @( posedge clk ) disable iff (~en)
        ( error_high >= error_low );
    endproperty

If not what it the proper way to check that 10 bits value of error_high MUST always be higher or equal the 10 bits value of error_low?

Thank you

2

In reply to Ep1c F4iL:

What makes you doubt this code?

3

In reply to Ep1c F4iL:

//if you want to consider reset also


    logic [9:0] error_low;
    logic [9:0] error_high;
    property error_low_greater_than_error_high;
      @( posedge clk ) disable iff ( reset && ~en)
        ( error_high >= error_low );
    endproperty

//Add this line to assert property
error_low_greater_than_error_high_assert :assert property (error_low_greater_than_error_high)
                                          else
                                          $display("@%d ns Assertion Failed",$time);