Assertion execution region in program block

SystemVerilog
1

Hi could you please provide the clarification for the below one.

assertions mentioned in module are sampled in prepone region . and they are executed in observed region . if the assertions are placed in program block, please let me know which region they are executed, because program block is executed in reactive region.

2

In reply to srbeeram:

The scheduling semantics of concurrent assertions are always the same whether they are instantiated in a program block or not.

Please forget about using program blocks.