Assertion to check timing parameter for memory interface

SystemVerilog
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1

Hi all,

I’m trying to check timing parameters of memory device.
Since the timing parameters are specified in picoseconds and they are not related to the clock, I think I need to make the checkers by using $time, or something else.

How can I describe the checkers by not using clock when the spec. is as below?
“Signal A must be low for minimum 50ps after it falls.”

I wrote the checker as below.
property A_width_check;
   realtime A_fell, A_width; 
   ($fell(A), A_fell = $time) |-> ($rose(A), A_width = $time - A_fell) ##0 web_width >= 50ps;
endproperty

I have no idea if the checker is described in a right way, and how I can check the result of property on Synopsys Verdi.
(I want to used “A_CHECKER: assert property” to check the result on Verdi, but compile error occurs since there’s no clock)

Thank you.

Best regards,
SJ Kim

2

In reply to soojin kim:

I would recommend using SDF annotation and simulation instead of trying to use assertions. SDF annotation is designed specifically to address what you want to accomplish.

3

In reply to soojin kim:

Usually it uses timing check task to check a duration of events as time.
In your case, use %hold timing check task.
Below is simple sample.


`timescale 1ps/1ps
module check(input in1);

  specify
    $hold(negedge in1, posedge in1, 51);
  endspecify

endmodule

Then, attach check module to DUT using “bind” struct.