Assertion to check signal stability for 1.5 clock cycles

SystemVerilog
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1

I want to check the stability of a signal once it goes high for 1.5 clock cycles.
The signal will only get sampled at the rising edge. So, the check can be something like, at each posedge of clock, if the signal has changed, assert if it’s not stable for the next rising edge as well as the next 2 falling edges.

But I am not sure how to check for 2 falling edges within a rising edge block.
Can anyone please help?

Thanks.

2

In reply to AbyD:
If you have a clock, how could you NOT have a falling edge?


// I want to check the stability of a signal once it goes high for 1.5 clock cycles.
// The signal will only get sampled at the rising edge. 
  bit a;  
  ap_stable1_5: assert property(@(posedge clk) $rose(a) |-> ##1 @(negedge clk) a); 
// ##1 is one clock, the @(negedge clk) is the half clock, thus the 1.5 clk where a==1
//-----------------------
/* Am assuming that the clock is symmetrical.  If asymmetrical, use the #half_period to create a negative clock. */

always  @( posedge ) begin 
    clk_f <= 1; 
    #half_period clk_f <= 0;     
  end
ap_stable1_5: assert property(@(posedge clk) $rose(a) |-> ##1 @(negedge clk_f) a);