Assertion to check if a signal is sampled atleast three times

SystemVerilog
, ,
1

I want an asserion to check whether any change in signal d is sampled by clk atleast 3 times. Is this the correct approach to do this?


property d_stable_check;
logic data1;
@(d)
(!$isunknown(d), data1 = !d) |=>
@(posedge clk)
(d == data1) ##1 (d == data1) ##1 (d == data1) ;
endproperty : d_stable_check
a_doublesync3:assert property(d_stable_check);
2

In reply to svishnu:

Hi,

I did not exactly understand what are you trying to do. Could you please frame it in a better way so that I can help you out?