Assertion binding across modules

SystemVerilog
,
1

Hi,
I have an assertion in a top level module that looks something like this.

assert (ModA.SigA != ModB.SigB) $error(…)

This is working so now I want to put this into a bind file and that is not working.

inside my bind file I’m trying

input ModA.SigA;
input ModB.SigB;

assert (ModA.SigA != ModB.SigB) $error(…)

but the compiler complains about the input declarations.
It tells me
… near “.”: syntax error, unexpected ‘.’, expecting ‘;’

How do I get the bind file to know about the hierarchy so I can implement this assertion there?

2

In reply to JSHammond:

The bind construct was designed to insert a unit at a specific place in the hierarchy. It will not help if you are trying to assemble signals from all over the hierarchy.

If you are trying to create re-usable assertion modules, you can still create that and connect its ports from different places in the hierarchy. For example

module check_equals(input bit W, X, Y, Z);
  ...
  assert (X != Y) $error(...);
endmodule

module top_mod;
   ...
   check_equals ck1(ModA.SigB, ModA.SigA,ModB.SigB, ModA.SigC);

endmodule

If you want to connect to many singles in one specific place in the hierarchy, then you can use bind to shorten the pathnames, but you can still use hierarchical references where needed.


module top_mod;
   ...
   bind check_stuff DUT.ModA, ck1(SigB, SigA, top_mod.ModB.SigB, SigC);
endmodule