Assertion

SystemVerilog
,
1

can any one explain how to write different delay in assertion like

property MEM_WRITE(logic bit[2:0]cycle);
@(posedge clk)
(~wen) |=> ##cycle addr!=($past(addr,cycle));
endproperty

ADDRESS:assert property (MEM_WRITE(wr_cyle)) else $display("ASSERTION FAILED ADDRESS IN NOT CHANGING"); //wr_cyle is defined as 5 (exp : 1 cycle write operation and 5 cycle no operation for same address 6 clock cycle need to write //for one address)

//or can i write like this //
property MEM_WRITE;
@(posedge clk)
(~wen) |=> ##[1:8] $changed(addr);
endproperty

ADDRESS:assert property (MEM_WRITE) else $display(“ASSERTION FAILED ADDRESS IN NOT CHANGING”)
///////////////////////////////////////

2

In reply to LOHIHTHA DM:

If you want to use dynamic delays or repeats, use my package (item 2 in my signature below)
The link to the package also provides examples.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy