Assertion

i have an assertion where in i have to check if A signal is having value 2 before the event checkA and if A is having vlue 6 after event checkA
i also want to check this value with clock pulse named clk…

i wrote my assertion as ,

property p;
@ (posedge clk) $rose(checkA)|-> (($past(A, 2) == 2) && (A == 6));
endproperty 

a : assert (p)

this is not working …
Can you help ?

In reply to rtawade:

You have to be more clear about what you mean by “before” and “after”. If you mean exactly one clock cycle before and after, then changing to a non-overlapping implication |=> will do that for you.

In reply to dave_59:

Or possibly


@ (posedge clk) $rose(checkA)|-> ($past(A, 2) == 2) ##1 (A == 6));
// and at he next cycle A==6
endproperty 
 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy