Assert number of toggle within a time duration

SystemVerilog
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1

how to assert that my output is toggeled 9 times after a certain amout of clocks like in the following pic

943×350 2.03 KB

i imagine the property to be like that
property output_check;
@ (posedge system_clk)
$rose(enable) ##560 (output toggeled 9 times);
endproperty

where 560 is the number of clock cycles ( duration ) where the output is expected to toggle 9 times

2

In reply to bassem yasser:

Can you try this?


property output_check;
int count;
@(posedge system_clk) disable iff(!resetn);
($rose(enable), count = 1) |-> first_match(($rose(enable), count = count + 1)[*1:560] && (count == 9));
endproperty
3

In reply to chris_le:

thanks a lot i am trying it now , but can you explain how it works ? and what does first match do

4

In reply to bassem yasser:

Hope the code works. Because the consequent may have multiple matches, then I use first_match. Please see the clarification of Ben: Clarification on first_match() | Verification Academy

5

In reply to chris_le:

> What is the original requirement? At least or at most 9 times toggle?
If the requirement is for AT LEAST 9 toggles then above solution will work just fine. If the requirement is for AT MOST 9 times then above solution may not be right as it doesn’t check for that condition.