Array sum with at least one element as multiple of 7

SystemVerilog
,
1

Write a constraint to an array
1.array elements sum=50
2.at least one element should be multiple of 7
3.we need to come up with constraint for array size based on above two constraints


module multi7;
  class mul7;
    rand bit[5:0] a[];
    constraint c1
    {
      a.size() inside {[2:44]};
      a.sum with (int'(item)) == 50;
      a.sum with ((item%7==0) >= 1) == 50;//this constraint is wrong and not getting multiple of 7
      
    }
  endclass
    initial begin
      static mul7 m1=new;
      m1.randomize();
      //$display("values:%p",m1.a);
      foreach(m1.a[i])
        $display("%d ",m1.a[i]);
    end
endmodule
2

In reply to dve12:

A couple of things to fix your problems :

1st, the correct way of writing what you want is the below :

a.sum with (int'(item%7==0)) >= 1;

(This is how you construct it : If the element is a multiple of 7, add 1 to the sum. 'int(item%7==0) returns 1 when it’s a multiple, 0 otherwise. Total sum should be atleast 1)

2nd, you will need to account for 0 being a multiple of 7. (if you don’t want 0s, remove them)

foreach(a[i]) (a[i] != 0);