2D array

SystemVerilog
1

Hii…
there is a typedef → typedef bit[31:0] a;
there is another typedef → typedef a[7] b;
will ‘b’ be one dimensional array( [31:0] b [7] ) or two dimensional array ( b[31:0][7])

2

In reply to Santoshi Nallapati:

typedef a[7]b is a packed array which will be equal to bit[31:0][0:6]

3

if we use this so “b c[$];”
then c is ?

4

In reply to Santoshi Nallapati:

Then it is equivalent to bit[31:0][0:6]c[$]

5

Thank you