SV :bus driving case

SystemVerilog
2

Following is drive task to get same behavior.

  task drive();
   
    @(posedge clk);
       begin
         repeat(10)
              begin
              cmd<=1'b1;                           
              wr_data<=$random();
                #2 $display("[%0t] cmd=%d wr_data=%h rd_data=%h",$time,cmd,wr_data,rd_data);
              //end
         
              //begin
              cmd<=1'b0;
               @(posedge clk);
                begin
                  rd_data<=$random();
              #2;
                 end
             $display("[%0t] cmd=%d wr_data=%h rd_data=%h",$time,cmd,wr_data,rd_data);
               end
       
      end
   endtask