Thank you: Dave, Christoph and Rsignori92,
Changed the clock signal to be 2-state type bit.
bit _clk;
And the CLK_PERIOD to be realtime.
// Clock Cycle periods
realtime CLK_PERIOD = 2083.33333ps; //in psec units; //frequency=480MHz
And will read on heartbeat and timeouts provided by UVM → thanks!
Some additional questions:
-
How and where it is better to randomize the CLK_PERIOD,
so I can pass it to through the uvm_config_db to the whole DV environment?
Since my clock generator code resides inside the TB module in the initial begin end statement. -
I saw on the web examples of other clock generators, with high_period and low_period and also clock enable, and skew and phases.
Is anyone familiar with a common code for clock generator that can be downloaded from the Verification Academy site or other sources?