Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Emulation User Forum 2020 | Bengaluru & Hyderabad
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - December 2019
      • Verification Horizons - June 2019
      • Verification Horizons - February 2019
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
Ask a Question
Coverage
  • Home /
  • Forums /
  • Coverage /
  • How to split a variable width using single coverpoint?

How to split a variable width using single coverpoint?

Coverage 373
coverpoint 13 functional coverage 14 System Verilog 3
jagan413
jagan413
Full Access
5 posts
December 13, 2016 at 12:51 am

hi,

Below is the snippet code related to coverage

bit [15:0] data_in;

covergroup cg;
INPUT_DATA0 : coverpoint data_in[3:0] { bins data0[] = [4'h0:4'hF] };
INPUT_DATA1 : coverpoint data_in[7:4] { bins data1[] = [4'h0:4'hF] };
INPUT_DATA2 : coverpoint data_in[11:8] { bins data2[] = [4'h0:4'hF] };
INPUT_DATA3 : coverpoint data_in[15:12] { bins data3[] = [4'h0:4'hF] };
endgroup:cg

In the above example, four coverpoints are used to the same variable.
Can it be possible to work around with a single coverpoint? Please suggest me, if any other possible solution.

Thanks in advance,
Jagan Kudimi

Replies

Log In to Reply

Solution

Solution

dave_59
dave_59
Forum Moderator
7301 posts
December 13, 2016 at 9:49 am

In reply to jagan413:
It's possible. But why? It would be much more complicated (you would need to expand out the ... in the example below.

covergroup cg;
  coverpoint data_in { 
         wildcard bins data0[] = {'h???0, 'h???1, ..., 'h???F},
         wildcard bins data1[] = {'h??0?, 'h??1?, ..., 'h??F?},
         wildcard bins data2[] = {'h?0??, 'h?1??, ..., 'h?F??},
         wildcard bins data3[] = {'h0???, 'h1???, ..., 'hF???}
};
endgroup:cg

- Dave Rich

jagan413
jagan413
Full Access
5 posts
December 13, 2016 at 10:23 pm

Hi Dave,

Thanks for reply.

I tried your suggestion and as you said it is laborious to expand each bin. It is fine now because the width of coverpoint is 16-bit. If the width of coverpoint changes to 32-bit then it will require more effort to expand each bin.

The reason I am opting for splitting input data because as the input data width of 16-bit so it will have 2^16 combinations. I don't want to cover 2^16 possible values. So I divided input data into four 4-bits so that each 4-bit needs to cover 2^4 possible values.

Regards,
Jagan Kudimi

Srini @ CVCblr.com
Srini @ CVCblr.com
Full Access
238 posts
December 14, 2016 at 2:14 am

In reply to jagan413:

Jagan,
Try using a covergroup with arguments and pass various data slices to different instances (You will need a wrapper class around covergroup).

Good Luck
Srini
www.verifworks.com

jagan413
jagan413
Full Access
5 posts
December 15, 2016 at 2:42 am

Thanks srini for suggesting alternate solution

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock