Hi,
Is it possible to disable a covergroup or a coverpoint in SV after coding the coverage, i need to disable or make it not to be part of my coverage without modifying the actual coverage code.
Thanks,
Jaswanth
In reply to jaswanth_b:
Most tools allow you to specify coverage exclusions when post-processing your coverage metrics. You should refer to your tool documentation or contact your vendor support team for additional assistance.
In reply to jaswanth_b:
You can also set the weight of a covergroup/coverpoint to 0 from within your SystemVerilog testbench.
In reply to dave_59:
Hi Dave,
Can we set the weight to 0 from outside or some top hierarchy like uvm test. Instead of changing the actual cover group code.
Thanks
Jaswanth
In reply to jaswanth_b:
Yes, you can do it by the covergroup type, or by instance if you have handle to the covergroup instance. See section 19.7 Specifying coverage options in the IEEE 1800-2017 SystemVerilog LRM.
In reply to dave_59:
Hi Dave ,
Section 19.7 Specifying coverage options of the LRM says :
Other instance-specific options can be assigned procedurally after a covergroup has been instantiated
covergroup gc (int maxA, int maxB) @(posedge clk) ;
a : coverpoint a_var;
b : coverpoint b_var;
endgroup
...
gc g1 = new (10,20);
g1.option.comment = "Here is a comment set for the instance g1";
g1.a.option.weight = 3;
Here weight is set procedurally at same time as covergroup is instantiated .
Is it also possible to set the weight after some time or after sampling the covergroup ?
In reply to MICRO_91:
Assuming you’re not going to look at coverage until after the end of the test, then you only need to set the instance based weight sometime between the construction of the instance and the end of the test.
If you are only doing type based covergroups, which is the default, then you only need set the weight before the end of the test.