Covergoup error

Coverage
1

Hi everyone,

I would like to collect the coverage from my simulation. I created the covergroup inside my verification module. The problem is when the coverage block is enabled (En_blockname_cov == 1’b1),the compilation takes too long I feel like it will not terminate, no warning just stuck somewhere .But once the coverage block is switched off, compiling the project is very fast only takes few seconds.
Please tell me how to improve this code and eliminate problem.
The section of the code causing the problem is the following:



module verif_XBar(
		  ...
		 );
	...			 				 
if(En_blockname_cov) 
     begin
       covergroup cg_blockname @(posedge clk);
 
             coverpoint {.............} 
				{
				bins ...;
				...
				bins blockname_invalid = default;
				}
             ...
       endgroup : cg_blockname
       cg_blockname blockname_cov = new();
     // real cov_blockname = 0.0;

       always @(posedge clk)
            begin
              blockname_cov.sample();
	   // cov_blockname = $get_coverage();	 
            end 
   end
endmodule

Thanks

2

In reply to vico:

This may help you

https://verificationacademy.com/forums/systemverilog/how-define-condition-covergroup-using-iff

3

In reply to vico:

Hi Vico,

Even if you are not getting any compilation error, I think semantics used here is causing the problem.

covergroup cg_blockname @(posedge clk); 
  coverpoint field_name iff(En_blockname_cov)
  {
    bins ...;
    ...
    bins blockname_invalid = default;
  }
  ...
endgroup : cg_blockname

cg_blockname blockname_cov = new();

Here, as you are using sampling condition in covergroup definition itself, no need to call sample method and separate always block for that. In code above, sampling will be done at each posedge of clock only when ‘En_blockname_cov’ is true.