Not exactly sure how you want the condition to affect the covergroup, but maybe you simply want to use the condition when you construct the covergroup.
You cannot use iff in the declaration of a covergroup. Please re-read this entire thread, then post the code you are trying to use and the error message you are getting.
This isn’t correct either. iff is only a guard against sampling a covergroup/point/bin. It has no place in construction. The with clause gets used in defining bins.
From SV_LRM std 1800-2017, 19.5.1 Specifying bins for values
The expression within the iff construct at the end of a bin definition provides a per-bin guard condition. If the expression is false at a sampling point, the count for the bin is not incremented.
//This is working fine for me. i am able to dump the correct collected coverage value also.
cp : coverpoint type_a {
bins out_bound_pqr[] = {[10:18],[37:45]} iff(type_a == PQR);
bins out_bound_xyz[] = {5,[10:18],25,[37:45]} iff(type_a == XYZ);
}
You can use `define for anything&mdash the macro pre-processor does not care about SystemVerilog syntax. But the end result has to be valid SystemVerilog to finish compilation.
In reply to Rahulkumar Patel:
You can collect coverage, but the calculation is incorrect.
The problem here is the bin gets created unconditionally, but is never incremented. If the expression is false at a sampling point, the count for the bin is not incremented.
Yes,bin gets created unconditionally.
Bin is incremented if expression is true and is not incremented when expression is false.
I think you are confusing the goal behind the original question. This is why it’s usually a better practice to start a question in a new thread than tacking on to an existing question.
I believe they want conditional bin construction, not conditional sampling. Otherwise you wont up unable to get 100% coverage of your coverpoint.