Automating the coverpoints

Coverage
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1

I have a situation where I need to Check if v_reg_btb_entry_XX_EN signals goes from 1->0. (Where XX varies from 0 to (btbdepth-1)). can someone help me how can I parameterize the covergroup so that it will create a coverpoint for each signal(v_reg_btb_entry_0_EN,v_reg_btb_entry_1_EN,v_reg_btb_entry_2_EN…v_reg_btb_entry_(btbdepth-1)_EN)?

2

In reply to Jyothi_G:

Try on similar line

https://verificationacademy.com/forums/coverage/how-get-array-coverpoints

3

In reply to sa5691:
In my case the name of the signal will vary.

4

In reply to Jyothi_G:

The SystemVerilog language does not let you index/parametrize into variable where numbers are embedded in the variable name. You would have to do this using a text editor to help you replicate the code.

Note that in this case, most tools have toggle coverage built-in and you could use a wildcard to specify the signal names for the specific transitions you are looking to cover.