Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • RISC-V Design - Webinar
      • Exploring Formal Coverage
      • Processor Customization
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar
    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings
    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - July 2023
      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us
    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
Ask a Question
Coverage
  • Home
  • Forums
  • Coverage
  • How to get array of coverpoints

How to get array of coverpoints

Coverage 562
prasads
prasads
Full Access
6 posts
October 11, 2013 at 2:36 am

I have an array of pointers, say ptr[192], each of its element can take 3 values 0,1,2.
How do i define the coverage for the complete array? Can I do something like:

generate for(i=0;i<192;i=i+1) begin
coverpoint ptr[i] { bins ptr_val[3] = {0,1,2}} ;
endgenerate

Replies

Log In to Reply

Solution

Solution

dave_59
dave_59
Forum Moderator
11281 posts
October 11, 2013 at 9:11 am

You can't use a generate statement inside a covergroup. But you can declare an array of covergroups each with a single coverpoint:

   bit [1:0] ptr[192];
   covergroup ptr_val_cg(ref bit [1:0] ptr);
      coverpoint ptr { bins ptr_val = {0,1,2};}
   endgroup 
 
   ptr_val_cg ptr_cg[192];
   initial begin
      foreach (ptr[i])
	ptr_cg[i] = new(ptr[i]);
   end

— Dave Rich, Verification Architect, Siemens EDA

itsmyturn
itsmyturn
Full Access
32 posts
October 27, 2015 at 12:50 pm

In reply to dave_59:

Hi Dave,

I ran into the same issue. How do we make your solution work for a case where we want to cross the individual coverpoints (of the array) with some other coverpoint? We can't cross coverpoints from different covergroups right?

Thanks,
Satish

dave_59
dave_59
Forum Moderator
11281 posts
October 27, 2015 at 8:47 pm

In reply to itsmyturn:

This would be difficult to specify for an array, even if you were allowed to cross coverpoints from different covergroups.

It might help to explain what you are looking for coverage of. There might be a simpler approach using a function with some other code around it.

— Dave Rich, Verification Architect, Siemens EDA

itsmyturn
itsmyturn
Full Access
32 posts
October 28, 2015 at 10:10 am

In reply to dave_59:

The tool we're using doesn't support array of covergroups :). I also felt it's easier to look at coverage results if the coverage of the whole array is in one covergroup as opposed to looking at an array of covergroups. I'm just trying to write coverage for a multidimensional array and I'm trying to avoid typing all the entries of the array.

dave_59
dave_59
Forum Moderator
11281 posts
October 28, 2015 at 10:43 am

In reply to itsmyturn:
SystemVerilog does not support arrays of covergroups embedded in classes. If that is your issue, you can define the covergroup outside the class, or you can create an array of classes with the covergroup embedded. Unfortunately, SystemVerilog covegroups were only designed to deal with integral types, not arrays.

It would really help to see the examples of what you are trying to cover.

— Dave Rich, Verification Architect, Siemens EDA

itsmyturn
itsmyturn
Full Access
32 posts
October 28, 2015 at 1:43 pm

In reply to dave_59:

My covergroup is inside a module and not a class. I'm trying to cover all values of this counter variable(for all combinations of the higher dimensions).
logic [4:0][7:0][2:0] counter;

The [4:0] dimension is one hot (so, it can hold 5 values)
The [7:0] dimension is one hot (so, it can hold 8 values)
The [2:0] can be any value (it's not decoded) and is what will be my coverpoint variable.

So, I'm trying to see if there's a way of writing these 40 coverpoints without typing each of them. Please let me know if what I wrote above isn't clear. Thanks for the help.

gaurangchitroda
gaurangchitroda
Forum Access
1 post
October 08, 2019 at 11:36 am

In reply to dave_59:

Hi Dave,

As per my understanding, taking "array of covergroup inside a class, with covergroup definition outside class" is a valid SystemVerilog semantic.
Can you please confirm about the same? Also, it would be great if you can point to or copy paste the LRM description for the same. I could not find the exact mention about this in LRM.

Best Regards,
Gaurang

dave_59
dave_59
Forum Moderator
11281 posts
October 08, 2019 at 2:22 pm

In reply to gaurangchitroda:

It's because of this stamenent

section 19.4 of the 1800-2017 LRM wrote:
A covergroup declaration within a class is an embedded covergroup declaration. An embedded covergroup declaration declares an anonymous covergroup type and an instance variable of the anonymous type. The covergroup_identifier defines the name of the instance variable.

There's no syntax that allows you to declare any array of instance variables with this anonymous type.

— Dave Rich, Verification Architect, Siemens EDA

mseyunni
mseyunni
Full Access
194 posts
March 02, 2020 at 7:27 am

In reply to dave_59:

Hi Dave,

Is the restriction of "one cannot have array of covergroups is only for a class?" or does it apply for a module as well?

I meant, can we have array of covergroups inside a module?

Thanks,
Madhu

dave_59
dave_59
Forum Moderator
11281 posts
March 02, 2020 at 9:39 am

In reply to mseyunni:

You can instantiate an array of covergroups anywhere you can instantiate a single covergroup instance. The only restriction is you can't declare a covergroup inside a class and instantiate an array of that same covergroup.

— Dave Rich, Verification Architect, Siemens EDA

rajivdesh
rajivdesh
Full Access
38 posts
May 02, 2020 at 10:33 am

In reply to dave_59:

in the below EDA link , i am getting the error , that array of covergroup instances cannot be created .

https://www.edaplayground.com/x/2vPa

Can you please explain me why is it so ?even if system verilog supports it

dave_59
dave_59
Forum Moderator
11281 posts
May 02, 2020 at 12:09 pm

In reply to rajivdesh:

You picked the one older simulator that doesn't support this yet.

You have a bunch of other errors. See https://www.edaplayground.com/x/2SJi

— Dave Rich, Verification Architect, Siemens EDA

irshad_mansur
irshad_mansur
Forum Access
6 posts
February 18, 2021 at 11:17 pm

In reply to dave_59:

Hi Dave,
How can we do cross coverage in below case. I want to do cross coverage between coverpoint xyz and all the elements of ptr_cg.

bit [1:0] ptr[192];
   covergroup ptr_val_cg(ref bit [1:0] ptr);
      coverpoint ptr { bins ptr_val = {0,1,2};}
   endgroup 
   class cov_mon
     ptr_val_cg ptr_cg[192];
     int xyz;
     function new();
      foreach (ptr[i])
	ptr_cg[i] = new(ptr[i]);
     endfunction
     covergroup new_cg();
       coverpoint xyz;
     endgroup
   endclass
   end
dave_59
dave_59
Forum Moderator
11281 posts
February 19, 2021 at 9:49 am

In reply to irshad_mansur:

You cannot cross coverpoints between different coverpoints. You can put the coverpoint xyz inside the same covergroup by making it another argument of ptr_val_cg.

bit [1:0] ptr[192];
   covergroup ptr_val_cg(ref bit [1:0] ptr, int xy);
      coverpoint ptr { bins ptr_val = {0,1,2};}
      cross ptr,xy
   endgroup 
   class cov_mon
     ptr_val_cg ptr_cg[192];
     int xyz;
     function new();
      foreach (ptr[i])
	ptr_cg[i] = new(ptr[I],xyz);
     endfunction
   endclass
 

— Dave Rich, Verification Architect, Siemens EDA

boss8032
boss8032
Full Access
15 posts
September 26, 2023 at 9:48 am

In reply to dave_59:
can we have another way to do this ?

Siemens Digital Industries Software

Siemens Digital Industries Software

#TodayMeetsTomorrow

Portfolio

  • Cloud
  • Mendix
  • Electronic Design Automation
  • MindSphere
  • Design, Manufacturing and PLM Software
  • View all Portfolio

Explore

  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Customer Stories
  • Partners
  • Trust Center

Contact

  • VA - Contact Us
  • PLM - Contact Us
  • EDA - Contact Us
  • Worldwide Offices
  • Support Center
  • Give us Feedback
© Siemens 2023
Terms of Use Privacy Statement Cookie Statement DMCA