In reply to AKASHNBHAGAT:
There are two key reasons:
[1] For code coverage every design is just a RTL Verilog code. It does not distinguish between the processor or network switch design. So if you want to cover the design intent like instructions of processor or packets switch you need the functional coverage
[2] Code coverage does not address the concurrency, combinations and sequences. Its only addressed by functional coverage
Google “code coverage pain points” for more information on this topic.