think i have a project with top module A
and inside the top module exists some submodules,such as
A_1, A_2, A_3, A_4,… A_n
while there are some sub-submodules exist in the submodule A_x ,such as
module : A_1_1 , A_1_2, A_1_3, …
A_2_1, A_2_2, A_2_3, A_2_4…
A_3_1, A_3_2, A_3_3…
…
A_n_1, A_n_2, A_n_3, A_n_4…
now, i want to use OVM to verification my project
does the verification engineers need to verification all the submodules of A_x_x with OVM?
or just verification some modules such as A_x with OVM, and
others ,say A_x_x, ues pin-level verification by logic engineers?
(i think use ovm to verification all submodules maybe time spended)
The structure you are describing is very general and also very common. However, many times several sub-modules are identical and can therefore be effectively tested with the same or similar tests, with OVM or any other method.
As for the level of verification, you get what you pay for: If you are able to write the higher-level tests such that they require by design the sub-modules to work correctly, then you don’t need to verify them separately. For example, if you have an encryption unit with a Fifo on the input and output side, then verifying the encryption engine from the outside will also verify the correct Fifo connections, otherwise it would not work at all.
However, it is rather difficult to verify all corner-cases for a sub-module if you are just using it as part of a larger test. In case of the input- and output-Fifos from the example above, it would be rather challenging to verify their correct behavior on the Fifo-full condition within a larger test environment which is optimized for best data throughput.
What you basically need is a test-plan and a verification goal. Then you can evaluate whether you are better off to use OVM, pin-level verification, or a mixture of both.