hi,
i was trying to write a simple adder function/task,which will take the length of inputs as an argument and then accordingly add them.
the code looks like this
function void add(input int len=8,input logic [len-1:0] a,input logic[len-1:0]b,output logic[len-1:0] sum);
but my compiler(Riviera-Pro) gives an error that lenshould be a constant.
i want to make a generic adder ,how can it be done?
i am using system verilog.
thanks in advance.
waris
In vectors you cannot use varaiable lengths, they should be constant, so to make them generic you need to define this constant using “parameter” or `define.
thanks for the reply.
i have tried that also.
but here also some errors are coming.
can you please give an example.
i know how to use parameters in a module but,i want to use this in a function.
any suggestions are welcome.
Hi, can we write parameterized task/function in systemverilog like template function in C++? Or it can be implemented using parameterized class in which parameterized task/function can be used? Is that right?
This is a frequently requested enhancement to Verilog/SystemVerilog. What you can do today is create a parametrized virtual class, and declare a static function/task inside the class.
virtual class C #(type T= int);
static function T add(T a, T b);
return (a+b);
endfunction
endclass
typedef bit [7:0] data_t;
typedef bit [15:0] address_t;
data_t X,Y,Z;
address_t A,B,C;
...
Z = C#(data_t)::add(X,Y);
C = C#(type(C))::add(A,B);
Dave Rich
The staticis so that you don’t have to construct a class object to use the task, and the virtual is so no one is allowed to construct the class.