Hi,
I do not have the solution, but I managed to isolate the problem.
As dsantos pointed out here some time ago, it is not just a virtual sequence problem, not even sequence-related problem.
Here is a compressed version of ovm_pkg:
package ovm_pkg;
class ovm_sequence_item; endclass
class ovm_sequence_base extends ovm_sequence_item; endclass
virtual class ovm_sequence #(type REQ = ovm_sequence_item) extends ovm_sequence_base;
REQ req;
endclass
endpackage
Now, what the user does is
module test;
import ovm_pkg::*;
class item extends ovm_sequence_item;
rand int a;
endclass
class seq extends ovm_sequence#(item);
item item0;
virtual task body();
req = new();
assert(req.randomize() with { a == -2; });
item0 = new();
assert(item0.randomize() with { a == -2; });
endtask
endclass
initial begin
seq seq0 = new();
seq0.body();
$display("seq0.req.a = %0d", seq0.req.a);
end
endmodule
If you copy&paste the above pieces of code into a single file and “vlog” it, you get the same
*** Warning: constraint.sv(26): (vlog-2223) Inline constraints for hierarchical call to randomize() will be resolved with respect to the current scope*
Moreover, if you’ll try to load it via vsim you’ll get
# ** Error: constraint.sv(26): Failed to find ‘a’ in hierarchical name.
The fact that
- seq inherits ovm_sequence which in turn inherits ovm_sequence_base which in turn inherits ovm_sequence_item &
- req field is declared under ovm_sequence as REQ(which should become item following the specialization) &
- item0 is declared under seq as item &
- the compiler only complains about not finding a under req(but not under item0 too)
makes me guess that, somehow, it(the compiler) forgot to update the type of req(which remained ovm_sequence_item, as default specialization). But this is merely a guess.
As a workaround, if you replace
assert(req.randomize() with { a == -2; });
with
assert(req.randomize() with { **req.**a == -2; });
you’ll still get the warning, but this time will work, i.e. run:
Loading work.ovm_pkg(fast)
Loading work.test(fast)
run
seq0.req.a = -2
VSIM 2>
