In reply to Reuben:
Hello Reuben,
Could you be able to share with me information regarding how to perform (steps) Gate Level Simulations, and commands that are to be used for GLS on Mentor Graphics or Other company EDA tools.
I have been looking for answers all over the internet but not able to find reliable source. I have developed verification environment using SystemVerilog and I have actually converted my RTL design into Gate level netlist but I want to know commands and steps involved in performing simple GLS.
regards,
Yogesh