Hi all, thanks in advance for suggestions/insights. I have a DUT with an internal module that allows access to an external 4GB memory. For simulation, I swap it out with a system verilog model. The model uses an associative array: logic [7:0] memory [logic [32:0]]; This works fine when the DUT…

My signature has a link to the trainings I offer. There’s a DVCon paper I wrote specifically about abstract/concrete classes. [image] Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection Downloads I’ve attached an updated version of co…

Testbench access to modify an associative array (used as a model for DUT memory)

UVM

dave_59 February 7, 2025, 12:10am 4

My signature has a link to the trainings I offer.

There’s a DVCon paper I wrote specifically about abstract/concrete classes.