I am trying to cover the active and inactive run-lengths of a signal.
I made a counter that increments when the signal is stable and resets on a transition.
always @(posedge clk) begin
if ($stable(sig))
counter <= counter + 1;
else
counter <= 1;
end
I thought I could then cover the “active” run-lengths by defining a coverpoint on the counter with the additional condition to only count it after the signal “fell” and similarly cover the “inactive” run-lengths with a coverpoint that only counts after the signal rises:
$rose/$fall will not work inside covergroup. Declare 2 variable eg : int sig_rise, sig_fall. Then in always block assign
if($rose(sig)) begin
sig_rise = 5;
counter <= counter + 1;
end
else if($fall(sig)) begin
sig_fall = 10;
counter <= 1;
end
Now capture the “active”/inactive run_length by checking the signal variable values.
coverpoint counter iff(sig_rise == 5) {
bins cycles = {1,2,3,[4:$]};
}
Try in this way.
I chose to simulate the functionality of $rose and $fell by maintaining a 1-cycle delayed copy of the signal for which I’m counting run-lenghts and looking at the difference between the 2.
Possibly for no other reason that SystemVerilog was designed by committee. It is very difficult for people who add features to the language to think of all possible interactions with every feature of the language.