In reply to ted.firlit:
In reply to ben@SystemVerilog.us:
My second question again seems like a common problem which I assume someone should have written a page of documentation regarding pairing assertions and cover statements, where the cover statements ensure the inputs to the logic are stimulated for all cases, and the assertion ensures that the outputs are correct for the given input conditions. Am I using assertions in a non-standard way? Or perhaps this is a basic occurrence which requires no detailed discussion. I was hoping to glean some hints on a “formula” for ensuring that I don’t miss something in my cover statement, based on a given assertion statement.
That might be your lucky day :)
It turns out that I did address this topic in my SVA Handbook 4th Edition; link provides pages from that book.
SystemVerilog.us/svabk4_coverage.pdf
Keep in mind that tools provide some coverage statistics on assertions (oassed, failed), but the cover property provides a more (see the pdf file).
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115