In reply to ted.firlit:
I have two questions related to coverage of Assertion Based Verification:
- What is the recommended way to report and observe that all coverage is at 100% while no assertions failed and no tests failed in the scoreboard? I would prefer to see a % reported for each module in our SOC, with all three of these items combined.
I see three ways to get coverage information:
- While in simulation, the tool (most, if not all simulators) provide those statistics.
- During the simulation run command, most tools provide a coverage report command that you can fire with various options. From Questa’s documentation, “The coverage report command produces textual output of coverage statistics or exclusions (e.g., assertions and cover groups). By default, the command prints results to the Transcript window, and returns an empty string. You can use the -file argument to save the output to a file”. See your simulator documentation for the specific command and options; this forum tries to be vendor independent, thus I won’t discuss the specifics.
- Use APIs. I address this topic in my book SVA Handbook 4th Edition, 2016 ISBN 978-1518681448. I am making those pages available at Functional coverage in verification. Code is provided in those pages.
- If I am using assertions to verify some of my output signals, such as asserting that an output is 1 only when enabled, and when a timer expires, it seems to me that I also need a cover statement to ensure the inputs have been stimulated in all conditions (enable is tested both low and high, and the timer signal has been expired & non-expired). Is there some documentation with examples of best practices for assertions and the corresponding cover statements?
- Asserting that an output is 1 only when enabled, and when a timer expires
- [Ben] That’s an assertion
- a cover statement to ensure the inputs have been stimulated in all conditions (enable is tested both low and high, and the timer signal has been expired & non-expired.
- [Ben] That looks like cover sequence of several types of sequences.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115