What is the recommended practice for instantiating a VHDL DUT from and ovm top and connecting it to an ovm_driver? Use a SV wrapper around the DUT with an interface port? Use elements of the interface as the actuals in the association list of the DUT component instantiation?
You got it.
I’m just starting to learn OVM and SystemVerilog. Could someone elaborate a little more in how to exactly accomplish this? I’m having a very difficult time finding practical examples of how to create a SV wrapper for a VHDL DUT.
Say I have a basic flip-flop VHDL entity defined as follows. How would you create a SV wrapper around this? None of the manuals or books I have talk about doing this.
ENTITY flipflop IS
PORT(D, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC;
END flipflop;
I really appreciate any help understanding how to do this!
The AVM cookbook has some examples that show hooking up a VHDL DUT with an SV testbench. See chapter 8 Stepwise refinement.
The Questa user guide has some examples mixing VHDL and SV code. It also shows how you can share package definitions that map SV structs and VHDL records at the port boundary.
Dave Rich
Not sure if my way is correct or not but I instantiate the VHDL directly in my SV testbench, with an instantation of the drivers interface, and direct connect the two up.
Seems to be working fine for me at the moment.
Whats the advantage of having a wrapper around the VHDL ???
Steve
Steve,
I thought “*wrapper”*was being used here to mean an SV testbench. You are correct that there is no need for an empty hierarchical container.
The only wrapper you might consider is when you have a Verilog or VHDL DUT without interface ports and your testbench assumes it has a DUT with interface ports.
Dave
module VDUT(input A, output B); // Verilog or VHDL DUT wthout interface
endmodule
module test; (itf ip); // test with interface port
endmodule
interface itf();
wire A; wire B;
endinterface
module Wrapper (itf ip); // wrapper with interface port
VDUT dut(ip.A, ip.B);
endmodule
module TB; // SV testbench withOUT using wrapper
itf ii();
VDUT dut(ii.A,ii.b);
test t(ii);
endmodule
module TB; // SV testbench WITH using wrapper
itf ii();
Wrapper dut(ii);
test t(ii);
endmodule
Ah, thank you! I think I’m starting to understand this now. I looked at the Questa User Guide as well as your example and I think I have the basic idea. So if I were to apply this to a flipflop DUT (for the sake of a simple example), would the following work?
(The Questa guide mentioned compiling VHDL with mixed language option so it can be imported into the SV file).
/*----VHDL entity( ffdut.vhd) -*/
entity flipflop is
port(D, Clock : in std_logic;
Q : out std_logic);
end flipflop;
/*-----------------------*/
(compile ffdut.vhd with "vcom -mixedsvvh")
/*------SystemVerilog--------*/
import ffdut::*;
module flipflop(input D, input CLK, output Q);
endmodule
module test (itf ip);
endmodule
interface itf();
wire D; wire CLK; wire Q;
endinterface
module TB;
itf ii();
flipflop DUT(ii.D, ii.CLK, ii.Q);
test t(ii);
endmodule
Ah, thank you! I think I’m starting to understand this now. I looked at the Questa User Guide as well as your example and I think I have the basic idea. So if I were to apply this to a flipflop DUT (for the sake of a simple example), would the following work?
(The Questa guide mentioned compiling VHDL with mixed language option so it can be imported into the SV file).
/*----VHDL entity( ffdut.vhd) -*/
entity flipflop is
port(D, Clock : in std_logic;
Q : out std_logic);
end flipflop;
/*-----------------------*/
(compile ffdut.vhd with "vcom -mixedsvvh")
/*------SystemVerilog--------*/
import ffdut::*;
module flipflop(input D, input CLK, output Q);
endmodule
module test (itf ip);
endmodule
interface itf();
wire D; wire CLK; wire Q;
endinterface
module TB;
itf ii();
flipflop DUT(ii.D, ii.CLK, ii.Q);
test t(ii);
endmodule
Hi Vance,
did you check…is this working?
As i am too in the same situation…looking for a solution.