Questasim not highlighting the syntext

OVM
1

Hello all…
In my Questasim 6.3d,source editor does not highlight the syntext for systemverilog source files with .sv extension .though it is working fine for vhdl/verilog.Anybody any idea?

2

I think a question like this should go to Mentor support where operators are standing by to take your call. Give them information like your Platform/OS and the way you invoked the source editor.

Dave

3

Ok.thank you.