PW OVM TESTBENCH AND OVC TEMPLATE GENERATOR

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Contributor: Stephen Donofrio Paradigm-Works
Date: April 16, 2009  
Description:

PW OVM TESTBENCH AND OVC TEMPLATE GENERATOR

The SystemVerilog FrameWorks Template Generator (SVF-TG) is a tool for generating a detailed boilerplate for an OVM based verification environment (testbench) from scratch based on user input.

- Generates OVCs and Testbenches
- Includes Makefile(s) that operates with Cadence and Mentor simulators out of the box
- Generates code that operates with either the SV package technique or include technique
- Generates virtual sequences and scoreboards
- Options for controlling the name of the project, tests, OVCs, number of agents, and bus monitors


Please download the OVM SVF-TG HTML Page to run the SVF-TG.

For feedback and issues contact us at svf-tg@paradigm-works.com

  
Download: pw_ovm_tg_0.htm