OVM wrapper for Verilog Bfms?

In reply to dave_59:

Dear Dave:

    Can you explain a little more about bind?
   In statement below:

    bind UART_TX:top.BLOCK[i].U_tx UART_TX_probe p()

    "UART_TX" is a module.
    "top.BLOCK[i].U_tx" is a scope
    "UART_TX_probe p()" is an instantiation.

    Totoally , What bind really want to do?

     If I dont want use bind, can it still achieve such function?

In reply to Jules:

is just a shortcut for instantiating a module (or interface) inside another module without modifying the source code for that other module. You can use all the concepts from the abstract class example here without using

In reply to dave_59:

The code is no more accessible. can I have the full working code for ovm wrapper for verilog bfm.

email: akulkarni@lateralsands.com


In reply to amtoya:

This site was moved recently and the file attachment links did not get properly updated.

Here are temporary links to the files:


In reply to dave_59:

This thread has been very helpful. Is there a UVM example for this implementation?

I have a DUT bfm with built in tasks that I want to access(register writes/reads etc). My approach is going to be as follows:

I create the abstract class with the pure virtual functions, and I extend the abstract class in the top module that has the DUT and the virtual interface. I do this here so I can get hierarchical access to the tasks in the bfm, instead of binding it. I store the extended class in the uvm_config_db so I can access it in the driver. My only concern would be that the driver won’t be able to see my extended class in the top module and I do not know how to address that. Please advise.

In reply to rthakur1:

This paper illustrates the same concepts and has been updated for UVM

In reply to dave_59:

This is exactly what I needed! Thank you! You’re a legend!