OVM wrapper for Verilog Bfms?

OVM
21

In reply to dave_59:

Dear Dave:

    Thanks!
    Can you explain a little more about bind?
  
   In statement below:

    bind UART_TX:top.BLOCK[i].U_tx UART_TX_probe p()

    "UART_TX" is a module.
    "top.BLOCK[i].U_tx" is a scope
    "UART_TX_probe p()" is an instantiation.

    Totoally , What bind really want to do?

     If I dont want use bind, can it still achieve such function?