OVM_FATAL @ 0: reporter [NOCOMP] No components instantiated...do i need test?

OVM
1

Hi All,
I m a newbee in this methodology…infact ovm is the first one i m trying…i have few questions…please reply

I’ll let you know bout my scenario…
First thing is that i have a multi language env. Some part of DUT is in VHDL and some in verilog.
Now in making a testbench with OVM i made files given below around DUT:

SV:-
Interface
Clk_generator

OVM Stuff:-
seq_item (ovm_seq_item)
sequencer(ovm_sequencer)
sequence_0 (ovm_sequence)
driver (ovm_driver)

Instantiated ,created and connected sequencer and driver in class ENV ectends OVM_env. Also i did set the default sequence with:
set_config_string(“sequencer”,“default_sequence”,“sequence_0”);

I skiped the stage of agent intentionaly as in my case i ws not seeing much use agent.

then i instatiated it all in the “module top” and called run_test(). Its giving error:

OVM_FATAL @ 0: reporter [NOCOMP] No components instantiated

as it first time i wrote any thing using OVM, please let me know:

  1. If the test class is mandatory step?
  2. if the set_config_string for changing the default_sequence is correct, if i want my sequence to be called only?
  3. What if i dont give set_config_string for setting default_sequence?

Thanks in advance

2

I have no run task in enviornment.
Just one run task i have that too in Driver class.

another doubt have;
Whether Agent is mandatory in OVM testbench ?

3

Hi secondlife,

Verification Environment is like a play ground, its upto user how he visualize’s the environment, builds it however he wishes and make the DUV “Design Under Verification” to play in the environment. Certain steps/procedures are already proven in many projects, so does people ask you to follow the same, as you can track out the issues in your environment. There is nothing called mandatory, its upto how you want the environment to be as per the Requirements.

Thanks,
Desperado → “:p”

4

Hi,
Where have you instantiated the ENV class?
You can write in this way:

module top()
env e;
initial
begin
e= new;
run_test();
end
endmodule

This should work fine…

Regards
Peer Mohammed
Kasura Technologies Pvt Ltd.
Bangalore

Hi All,
I m a newbee in this methodology…infact ovm is the first one i m trying…i have few questions…please reply
I’ll let you know bout my scenario…
First thing is that i have a multi language env. Some part of DUT is in VHDL and some in verilog.
Now in making a testbench with OVM i made files given below around DUT:
SV:-
Interface
Clk_generator
OVM Stuff:-
seq_item (ovm_seq_item)
sequencer(ovm_sequencer)
sequence_0 (ovm_sequence)
driver (ovm_driver)
Instantiated ,created and connected sequencer and driver in class ENV ectends OVM_env. Also i did set the default sequence with:
set_config_string(“sequencer”,“default_sequence”,“sequence_0”);
I skiped the stage of agent intentionaly as in my case i ws not seeing much use agent.
then i instatiated it all in the “module top” and called run_test(). Its giving error:
OVM_FATAL @ 0: reporter [NOCOMP] No components instantiated
as it first time i wrote any thing using OVM, please let me know:

  1. If the test class is mandatory step?
  2. if the set_config_string for changing the default_sequence is correct, if i want my sequence to be called only?
  3. What if i dont give set_config_string for setting default_sequence?
    Thanks in advance