hi friends,
i am new in ovm.i am not able to understand the meaning of
1.OVM ensures VIP interoperability across ecosystem and simulator.
2.OVM ensure plug and play functionality for designer
so friends do reply me.
thanks in advance
Hi Saurabh,
Thanks for asking, since these are two of the critical value statements for OVM. I’ll try to elaborate.
1.OVM ensures VIP interoperability across ecosystem and simulator.
The OVM was jointly developed by Mentor Graphics and Cadence, and so it has been tested and works on both Questa and IUS. The VIP Interoperability statement means that VIP developed on one simulator will work on the other, since both simulators support the same library. The library itself is released open-source as a single jointly-supported library, although both Mentor and Cadence ship simulator-specific versions (with enhancements to support debug and other features) with their simulators. From the user perspective, the API remains the same, so it doesn’t matter whether you develop on Questa, IUS, or any other SystemVerilog compliant simulator.
2.OVM ensure plug and play functionality for designer
The OVM was architected to support VIP reuse from project to project, and from block to system within a project. Through the use of
- TLM for inter-component communication,
- the built-in configuration mechanism,
- flexible component instantiation via the factory
- stimulus sequences independent of the testbench hierarchy
and other OVM features, you’ll be able to build VIP that will work in any OVM environment. As you’ll see in reading the documentation and other posts in this Forum, the OVM lets you create verification environments and testbenches that can easily reuse VIP developed by different teams and even different vendors. As long as you follow the development guidelines and be sure to take advantage of the functionality offered by OVM, with a little judicious planning, you’ll be reusing VIP all over the place.
Enjoy!