We need to verify some AXI-based peripherals in block-level (not SoC-level) testbenches. At first, we looked at ARM’s FRM (FileReaderModule), which is a file-based BFM – to use it in a simulation, you must run a pre-processing (perl) script to convert an ‘assembly-like’ .VEC file into intermediate-dataset for the FRM-verilog module.
As you can imagine, this operational paradigm is extremely limited – no branching, decision-logic, etc. no opportunity for in-testbench randomization/variation. Furthermore, the FRM is ‘self-contained’, out-of-the-box it doesn’t talk to the rest of the testbench. This makes co-ordinating testbench-events (like the peripheral sampling or generating external traffic) clunky. On the plus side, it looks very strong/well-suited for banging every corner of different sizes/geometries of AXI-transfers (except queued transactions.)
I was looking at the Cadence ABVIP offering at http://www.cadence.com/rl/Resources/datasheets/ocp_ds.pdf
The brochure mentions ‘OVM’ and uRM compliance. OVM is a long-term strategy for our team, but in the near-term, we don’t have any OVM/Systemverilog experts. So my questions are threefold:
(1) Is it appropriate for an OVM-component to be used in a non-OVM environment? (Can it be done at all?)
(2) What’s the overall learning curve of the ABVIP?
(3) In terms of stimulus-generation, can ABVIP handle directed-tests seamlessly? (Initially, we need to cover the basic types/sizes of transfers…later we’ll worry about sequences and such.)
(4) any other (OVM or not) solutions for AXI-peripheral verification?
EDIT
Ok, looking through the Incisive ABVIP datasheet more carefully, there’s no mention of stimulus generation. So I guess I misread it the first time around :o – does the AXI ABVIP come with both master & slave models?
You've identified some of the important issues to consider when selecting Verification IP. Cadence has been a leader in providing Verification IP for many years and has defined a set of criteria to use when making such decisions. The key is to both match your current needs and to anticipate your future needs as your environment and challenges grow.
The major factors/challenges to consider are:
How will you measure and ensure compliance with the protocol specification?
How can you initiate verification at the earliest possible time?
How will you reuse VIP when moving from block to chip or to system level verification or to derivative projects?
How can you achieve predictable verification closure? What metrics will you use to know when you’re done?
Will you need to verify multiple protocols in your design? How will you accomplish that?
Cadence provides Verification IP solutions to address the full spectrum of user needs. They deliver the highest quality, productivity and predictability available. Cadence’s VIP products include Assertion Based VIP (which is what you mentioned), advanced testbench VIP with fully automated compliance solutions, accelerated transaction based VIP, and hardware VIP for emulation (called SpeedBridges). Cadence’s advanced testbench VIP, called Universal Verification Components (UVCs) include a Compliance Management System (CMS) that automates protocol compliance verification. Each CMS includes pre-defined protocol specific verification plan and test suite. This relieves you the burden of writing many tests and manually predicting and tracking your progress. Furthermore, since Cadence UVCs are
fully metric driven, they ensure that your verification process is predictable and measurable. For an example of the value this approach provides see the ClearSpeed CMS Success Story.
Since you are verifying a block level DUT, the two classes of VIP that are most applicable for your immediate needs are the advanced testbench VIP (UVC) and Assertion Based (ABVIP).
To address your specific questions:
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Yes, OVM VIP can be used in a non-OVM environment. You will still benefit from the OVM capabilities built into the VIP. Of course you’ll get more value by using it in an OVM environment since you’ll be able to take advantage of functionality such as virtual sequences. By using a Cadence UVC you’d also be able to take advantage of the automated compliance solution (CMS) in either an OVM or non-OVM environment.
2.
The overall learning curve of the the UVC is measured in days to get started and couple weeks to get proficient. We have many examples of customers that began finding DUT bugs on the first day they installed the VIP.
3.
UVCs can handle the full spectrum of tests ranging from directed-tests to constrained-random generation. The key to productivity is to begin with the full CMS test suite to rapidly verify major functionality and increase overall coverage. From there you’d move to a more constrained-random and full-directed approach to attack corner cases. We strongly advocate using coverage metrics. They provide you with a “dashboard” to manage the overall verification process. By using CMS we will provide all that to you on a ready-to-go basis.
1.
Cadence's Assertion Based VIP (ABVIP) solution may also be applicable for you. AABVIP is targeted primarily for use with formal verification (IFV). ABVIP can be used by itself or in a complementary fashion to the UVCs. ABVIP is particularly well suited for design engineers to help them identify DUT issues even before a testbench is available.
As you can see Verification IP has many nuances. We encourage you to get in touch with a Cadence field representative to get you onto the most productive path for your needs.