Implement subscriber class with 2 analysis ports

Coverage
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2

Why did you not write

 virtual function void write_master(mester_sequence_item obj);
    ...
 virtual function void write_slave(slave_sequence_item obj);
    ...

or you could have done

uvm_analysis_imp_master#(cbc_sequence_item, coverage) master_imp;
uvm_analysis_imp_slave#(cbc_sequence_item, coverage) slave_imp;